1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a configuration of a level shifter circuit.
2. Description of the Background Art
A term “MOS” has been used in the past for a laminated structure of metal/oxide/semiconductor, and this is an acronym of Metal-Oxide-Semiconductor. However, especially in a field-effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), materials of a gate insulating film and a gate electrode are improved from a viewpoint of a recent improvement in integration and manufacturing processes.
For example, in the MOS transistor, a polycrystalline silicon has been adopted as the material of the gate electrode in place of metals, mainly from the viewpoint of forming self-aligning source and drain. Also, although a high-dielectric material is adopted as the material of the gate insulating film from the viewpoint of improving electrical characteristics, the material is not necessarily limited to oxides.
Therefore, the term “MOS” is not necessarily used exclusively for the laminated structure of metal/oxide/semiconductor, and in this specification also, such a limitation is not predicated. That is, in view of the common technical knowledge, the term “MOS” herein has a meaning not only as the ethymological acronym but also widely encompassing the laminating structure of conductor/insulator/semiconductor. Therefore, the term of MOS transistor is used in referring to an insulated gate field-effect transistor in which the gate electrode and the source/drain are electrically (galvanically) isolated.
FIG. 9 shows a conventional level shifter circuit LSC. The level shifter circuit LSC is a circuit for converting an input signal VIN to an output signal VOUT having a voltage level higher than that of the input signal VIN and outputting the same. The level shifter circuit LSC includes inverter circuits INV1 and INV2 acting as a pre-driver, a level shifter LS, and an inverter circuit INV3 which is an output driver.
The level shifter LS includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected in series between a power supply VDD2 and a reference power supply GND, and a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected in series between the power supply VDD2 and the reference power supply GND. A node ND01 is provided between the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and the node ND01 is connected to a gate of the P-channel MOS transistor P2. A node ND02 is provided between the P-channel MOS transistor P2 and the N-channel MOS transistor N2, and the node ND02 is connected to a gate of the P-channel MOS transistor P1. Also, a complementary signal corresponding to the input signal VIN is inputted to each of the gates of the N-channel MOS transistors N1 and N2 (transistors for input). The power supply VDD1 is supplied to the inverter circuits INV1 and INV2, and the power supply VDD2 is supplied to the level shifter LS and the inverter circuit INV3, and an equation of power supply VDD1 (low-voltage supply)<power supply VDD2 (high-voltage supply) is satisfied.
In the conventional level shifter circuit LSC shown in FIG. 9, a rising operation at the time of power activation is not sufficiently considered. That is, depending on an order of the power activation of the power supplies VDD1 and VDD2, an operation of the level shifter LS might be unstable. Next, the rising operation of the level shifter circuit LSC at the time of power activation will be described.
First, a case in which the power supply VDD1 rises before the power supply VDD2 will be described. When the power supply VDD1 rises, each voltage level of signals inputted to the gates of the N-channel MOS transistors N1 and N2 is either a high level (power supply VDD1) or a lower level (reference power supply GND) depending on an input voltage signal VIN, that is, complementary signals are inputted to the gates of the N-channel MOS transistors N1 and N2. Further, when the power supply VDD2 rises, each of the nodes ND01 and 02 is fixed to either voltage level of the high level (power supply VDD2) and the low level (reference power supply GND) depending on the signals inputted to the gates of the N-channel MOS transistors N1 and N2, and the level shifter LS operates in a stable manner (output signal VOUT is defined).
Next, a case in which the power supply VDD2 rises before the power supply VDD1 will be described. In this case, the complementary signals are not inputted to the gates of the N-channel MOS transistors N1 and N2, and a voltage condition of each of the nodes ND01 and ND02 is not stabilized, so that the operation of the level shifter LS becomes unstable (output signal VOUS becomes undefined).
That is, in the level shifter circuit LSC as in FIG. 9, in a state in which the power is activated and only the high-voltage power supply VDD2 rises, the complementary signal is not inputted to each transistor for input, so that there is a possibility that the output signal VOUT becomes undefined. Meanwhile, the normal operation of the level shifter circuit LSC (a case in which both of the power supplies VDD1 and VDD2 are supplied) is disclosed in FIG. 8 of Japanese Patent Application Laid-Open No. 2003-17996 to be mentioned later, so that this is not described here.
With regard to such an operation at the time of power activation, a configuration intended for assuring a stable operation irrespective of the order of power activation has been proposed.
In Japanese Patent Application Laid-Open No. 2003-17996, there is arranged a capacitative element or a resistance element between the high-voltage power supply or the ground and the input terminal of the transistor for input of the level shifter, as means for fixing the input signal to the transistor for input of the level shifter. As a result, a pass-through current at the time of power activation is prevented.
In Japanese Patent Application Laid-Open No. 10-84274, there is arranged a switch transistor at a differential circuit section at which a signal is converted to a high voltage of the level shifter circuit. By configuring to turn on and off the switch transistor in synchronization with the control of the low-voltage power supply, the signal at the differential circuit section is fixed, and the output status is fixed to a desired signal level by a pull up transistor or a pull down transistor provided on the output terminal, thereby preventing a condition in which the circuit output is undefined.
In Japanese Patent Application Laid-Open No. 2005-354207, an N-type transistor, which may be used for resetting at the time of turning off the internal power supply, is connected to two drain terminals of cross-coupled P-type transistors in the level shifter. With this configuration, output buffer false operation at the time of power activation is prevented.
Japanese Patent Application Laid-Open No. 05-7151 includes a current bypass circuit between a common drain end and a ground potential point of an MOS inverter on the output side. With this configuration, the output of the level shifter circuit is stabilized.
In this manner, attempts are made to stabilize the operation of the level shifter circuit at the time of power activation. However, in these documents, an area of the circuit added for the stable operation is not sufficiently considered.